1. Field of the Invention
The present invention relates to an electrostatic discharge circuit (ESD) with high triggering discharge providing good ESD protection and avoiding the latch up effect.
2. Description of the Related Art
Generally, in order to protect semiconductor chips from damage caused by high voltage generated from contact with objects with electrostatic charge (ESD) during the manufacturing process, there is an ESD protection circuit configured between the output port of the chip and the power supply port. Per requirement of the circuit, the ESD protection circuit should remain in an open state through normal operation so that the power supply port and the output/input port maintain normal functioning. It is only when the ESD occurs at an end of the ESD protection circuit that the circuit is in a short state for dissipating the ESD current to protect the internal circuit of the semiconductor chips.
The conventional ESD protection circuit can be divided into two categories. One features a bipolar transistor and the other utilizes the semiconductor control rectifier, SCR, as the primary component.
The bipolar junction transistor (BJT) usually consists of parasitic BJT of the source/substrate/drain of the MOS transistor at the output port. Since the output port of the MOS transistor requires extremely high driving forces, the parasitic BJT must be able to disperse large amounts of current when an ESD event takes place. However, for the ESD protection circuit between the input port and the power supply circuit, such a utility will result in a substantial increase in transistor size. Moreover, the holding voltage of the BJT is conventionally large, higher than approximately 7 volts. Therefore, a large ESD current will generate very high temperature in the BJT. If the ESD current only passes through part of the MOS transistor, the MOS transistor is easily overloaded and impaired. Thus, it is difficult to design an ESD protection circuit using BJT.
The ESD protection circuits at present mostly feature an SCR and have advantages of low holding voltage (app. 1.6 voltage), low triggering current and small size. Nevertheless, such an ESD protection circuit design has problems when undergoing ESD electromagnetic comparability (EMC) tests at the system-level. During the test, the ESD current at the output port is actually dissipated by SCR. However, if the voltage of the output port is close to 3 volts before the EMC/ESD test, then, after the EMC/ESD test, the SCR will hold the potential at the I/O port to the holding potential (app. 1.6 volt). This will result in the suspension of the whole system, may even burn a part of the semiconductor chip.